UV Curing PCB HV Creepage Distance and Tracking Design

UV Curing PCB HV Creepage Distance and Tracking Design

Abstract

The trigger, ballast and filter stages of a UV curing supply run at 5–20 kV on FR-4, and the board surface between those nodes changes chemistry under 200–450 nm light. The physical gap is fixed, and the electrical gap is not. This article gives the surface resistance, Joule heating and time-to-track arithmetic, four field failure modes, the derating and slot rules, and the leakage-current monitor that warns before the first flashover.

1. Einleitung

The high-voltage sections of a UV curing supply run at 5–20 kV, and their insulation depends on creepage distance: the shortest path along the board surface between two conductors at different potential. IEC 60664 and IPC-2221 give the minimum creepage for a pollution degree and a material group.

Those tables assume ordinary industrial air. Inside a curing machine the same board sees 200–450 nm photons, ozone, heat and cleaning solvents. The FR-4 epoxy oxidizes, the surface turns polar and hydrophilic, and airborne organics photopolymerize into a film that humidity makes conductive.

The physical distance never changes. The distance that actually holds off voltage does. That split explains the hardest fault to reproduce: a board that passed hipot and PD testing at the factory flashes over after a year, with unchanged geometry and no failed component.

This article gives the surface conduction and tracking arithmetic, the four field failure modes, the derating and slot rules, and the leakage monitor that turns a creeping surface into a measurable trend.

2. Kernmechanismus

2.1 Surface leakage resistance

A contaminated film between two conductors behaves as a resistor whose value follows the film geometry and the surface resistivity of the laminate.

R_s = ρ_s · d / w

where R_s is the surface leakage resistance, ρ_s is the surface resistivity of the aged laminate, d the creepage length between the conductors, and w the width of the conducting film. UV exposure and contamination drive ρ_s down one to three decades in one to three years, so a film that measured 50 MΩ when the machine was new reaches 5 MΩ or lower by the end of the warranty.

2.2 Joule heating and the tracking condition

Leakage current through a localized constriction of that film dissipates power in a few square millimetres of laminate.

P = I² · R_s

where P is the dissipated power, I is the leakage current and R_s is the surface leakage resistance. At 10 kV across the 50 MΩ film of §2.1 the leakage current is 200 µA and the film burns 2 W. Packed into a few square millimetres, that raises the surface above the 300 °C char temperature of the epoxy, and the char is conductive carbon.

2.3 Time to track against creepage distance

The time from a clean surface to a carbon bridge scales with the square of the creepage distance and inversely with the square of the applied voltage.

t_track = K · d² / (V² · σ_s)

where t_track is the time to a carbon track, K is an empirical constant for the laminate and finish, d is the creepage distance, V is the applied voltage and σ_s is the surface conductivity at end of life. Doubling the creepage quadruples the time. A 10 kV node with 25 mm of creepage tracked in 18 months in the field; the same surface reaches 6 years at 50 mm and 10 years at 65 mm.

2.4 Triple-junction discharge and monitor response

A second path opens where the capacitor body, the solder fillet and the board surface meet. Above the PD inception level, discharges erode the laminate and the outer glaze, and the pit concentrates field until it reaches an electrode. The leakage monitor that watches for this needs its own time constant.

τ = R · C

where τ is the monitor time constant, R is the series monitoring resistance and C is the node capacitance. With a 10 MΩ monitor and a 4700 pF node the constant is 47 ms, so the logged value is stable inside a quarter of a second.

Fig. 1 — At 10 kV a bare FR-4 node tracks in 18 months at 25 mm and needs 65 mm for ten years, while a coated slotted board crosses ten years near 37 mm.

3. Schwachstellen im Engineering

Pain Point 1: Margin erodes while the geometry stands still

The board passes hipot and PD testing at the factory, the creepage geometry never changes, and after a year of service the leakage current has tripled and the machine trips without a repeatable fault. No component has failed, and the surface has. This fault resists reproduction because it depends on accumulated UV dose.

Pain Point 2: Dust photopolymerizes into a conductive film

Airborne organics settle on the board in printing and coating plants, and UV light polymerizes them into a film that humidity makes conductive. A board that looks clean carries 50 MΩ between trigger nodes, and the film is invisible below high magnification.

Pain Point 3: The capacitor terminals become the weak point

A capacitor body is built for clean indoor service. Mounted on a degrading board, its terminal-to-terminal gap becomes the shortest path in the layout, and the field return names the capacitor while the board caused the stress.

Pain Point 4: Solvent cleaning accelerates the damage

Maintenance crews clean the boards with isopropyl alcohol and proprietary solvents. The solvent extracts plasticizers and leaves a residue, and the residue photo-crosslinks under the lamp. The cleaning step speeds up the degradation it was meant to remove.

4. Entwurfsschritte

Strategy 1: Derate the creepage table for UV service

Assume pollution degree 3 and add a UV factor. Multiply the IEC 60664 minimum creepage for the voltage class by 1.5–2× on boards that see lamp radiation. For 10 kV that gives 50–60 mm of surface path instead of the 25–30 mm table value.

Strategy 2: Cut routed slots between high-voltage nodes

A 5 mm deep slot between trigger nodes doubles the surface path at almost no cost. Specify routed grooves in the board outline instead of relying on solder-mask separation, because the mask collects the film that carries the leakage.

Strategy 3: Choose packages with body creepage

Wählen Sie ein N4700 disc or an HVCT8G screw-terminal part whose body height and glaze extend the path from the top of the capacitor to the board surface. Specify at least 20 mm of creepage on the capacitor body for the 10 kV class.

Strategy 4: Conformal coat the high-voltage zone

Apply a UV-stable, high-purity silicone conformal coating over the zone after assembly. The coating raises surface resistivity by 100× and blocks dust ingress. Silicone is the right chemistry here because it does not yellow or crack under the lamp, while a Folienkondensator elsewhere in the stage offers no protection to the board surface.

Strategy 5: Instrument the leakage current

Add a 10–100 MΩ Abtastwiderstand in the trigger supply and log the leakage trend. A doubling over six months is the earliest warning of surface degradation, and it gives time to re-coat or replace the board before the first flashover.

Strategy 6: Qualify the surface by UV aging

Age test coupons at 10× the operating flux for 500 h with bias applied, and measure surface resistivity every week. Accept a laminate only when its surface still measures above 100 GΩ after aging. A Dickschichtwiderstand in the divider chain sees the same surface, so qualify it in the same coupon.

Komponentenparameter	Typischer Wert	Testbedingung
Nennspannung (HVCT8G-Serie)	10 kV DC	Hi-Pot 1.5× für 60 s
Kapazität	4700 pF ±20% (472M)	1 MHz, 1 V<sub>eff</sub>
ESR bei 1 MHz	unter 50 mΩ	25 ° C
Schleifeninduktivität (E40-Sehne)	unter 8 nH	40 mm Anschlussabstand
Isolationswiderstand	über 10 GΩ bei 500 V Gleichstrom	25 °C, 60 % relative Luftfeuchtigkeit
Temperaturbereich	−40 °C bis +125 °C	IEC 60068-2-Reihe
Impuls-dv/dt-Fähigkeit	über 50 kV/µs	bei Nennspannung

5. HVC capacitors for UV-exposed boards

Three properties decide whether a capacitor helps or hurts the creepage margin: body geometry, surface chemistry and loss. HVC builds N4700 parts for all three.

Sechs Parameter, die hier von Bedeutung sind

• Disc and 441 screw-type bodies carry long surface paths from terminal to terminal, so the body adds to the board creepage instead of consuming it.
• N4700 (T3M) strontium titanate with a dense glaze surface takes up negligible moisture, which keeps the body surface resistivity high in a humid cabinet.
• tanδ at or below 0.1% at 1 kHz keeps the body cool, so it never drives the local laminate to the 300 °C char temperature.
• PD below 5 pC at 1.2× rated voltage removes the triple-junction erosion that normally opens the first pit at the capacitor footprint.
• ±30 ppm/°C and a full 1 kV to 100 kV range hold the same creepage and clearance layout across the trigger, ballast and filter stages.
• Field validation: an HVC 40 kV / 441 screw-type capacitor replaced a first-tier brand part in high-voltage field-service programs, and the same construction matches the electrical parameters of Vishay HVCC and KEMET radial-lead ranges.

Lieferung und Support

Standard parts ship in 4–8 weeks and matched sets in 6–10 weeks. HVC applications engineering reviews the board stack-up, the voltage nodes and the maintenance routine for the site.

Send the node voltages, the UV flux at the board, the creepage drawing and the cleaning method. HVC returns a creepage plan, a capacitor package with matching body creepage, and PD-certified samples for UV-aging qualification within two weeks.

6. Häufig gestellte Fragen

Q1: Why does a board pass hipot and fail after a year?

Because hipot measures the board it was built with. Surface resistivity falls one to three decades over one to three years of UV exposure, so the leakage current at 10 kV rises from a few microamperes to hundreds. Hipot at the factory cannot see that trend.

Q2: How much extra creepage does UV service need?

Multiply the IEC 60664 table value by 1.5–2× for pollution degree 3 with a UV factor. At 10 kV that turns the 25–30 mm table value into 50–60 mm of surface path, and the time to track rises with the square of that distance.

Q3: What does a 5 mm slot buy?

It doubles the surface path across the gap, so the time to track rises about fourfold. The slot also interrupts the film that carries the leakage, which is why a routed groove works better than extra solder-mask clearance.

Q4: Which warning comes first, leakage or PD?

Leakage. A 10–100 MΩ sampling resistor in the trigger supply logs the trend months before the first discharge, and a doubling over six months is enough evidence to re-coat the zone.

Q5: How much body creepage should the capacitor have?

Specify at least 20 mm of creepage on the capacitor body for the 10 kV class. Below that figure the terminal gap becomes the shortest path in the layout once the board surface ages.

Q6: Does conformal coating replace the creepage margin?

No. The coating raises surface resistivity by about 100× and blocks dust, and it still needs the derated distance underneath it. Design the distance first, then coat the surface.

7. Referenzen

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